The scaling of silicon integrated-circuit processing to deep-submicron feature sizes poses significant challenges for SOC (systems-on-a-chip) design. On the positive side, scaling increases the density and speed of digital CMOS (complementary metal oxide semiconductor). On the negative side, scaling burdens analog CMOS with low transistor-breakdown voltages, poor transistor matching, and limited dynamic range. SOC applications typically require deep-submicron CMOS for the digital circuitry, but have analog inputs and/or outputs. To enable mixed-signal SOC applications, engineers need a simple way to design precision analog circuits side-by-side with digital logic, in standard digital CMOS processes. One approach that holds huge promise is to use self-tuning transistors that adapt locally to improve circuit performance. If engineers had a simple means to incorporate local parallel adaptation in their silicon chips, they could greatly advance SOC performance and applications. Unfortunately, large-scale local learning in silicon has so far eluded researchers. A primary reason is the lack of a simple way to enable nonvolatile analog on-line adaptation in CMOS circuits.
Prior art floating gate transistors, which use electrical charge stored on a floating polysilicon gate embedded in an insulator such as silicon dioxide, provide suitable nonvolatile analog storage. The charge on such a floating gate is known to remain fixed for periods of many years. Although the advantages of using floating gate transistors as memory elements are well known, their application to silicon learning networks and analog memory cells has been limited. The principal reason has been the lack of suitable bidirectional and self-convergent mechanisms for writing the analog memory. Because the gate of a floating gate transistor is completely embedded within an insulator, writing the memory involves moving charge carriers through this insulator. Many mechanisms are known which will move electrons through an insulator. Two are tunneling and hot-electron injection.
The difficulty in transporting electrons across the barrier presented by the silicon/oxide interface is depicted in FIG. 1. Surmounting the barrier 10 requires that an electron possess more than about 3.1 eV of energy. At room temperature the probability that semiconductor electrons will possess this energy is exceedingly small. Alternatively, an electron could tunnel through this barrier; however, at the oxide thicknesses required for nonvolatile storage the tunneling probability is also exceedingly small.
Fowler-Nordheim (FN) tunneling involves applying a voltage across the oxide 12, as shown in FIG. 2 which enhances the probability of an electron tunneling through it. Tunneling current versus oxide voltage for a 400 Å SiO2 gate oxide typical of a 2 micron MOS (metal oxide semiconductor) process is shown in FIG. 3. Bidirectional currents through the oxide are required to achieve the learning and unlearning functions necessary in a silicon learning cell, and the writing and erasing necessary in an analog memory cell. Although the tunneling process has no preferred direction, bidirectional tunneling requires either dual polarity high voltages, or a single polarity high voltage and a means for pulling the floating gate to this voltage when adding electrons, and pulling it near ground when removing them. Both approaches are unattractive. The dual polarity solution requires a negative voltage much lower than the substrate potential; the single polarity solution does not support simultaneous memory reading and writing or self-convergent memory writes.
Single polarity bidirectional tunneling is often used in writing digital EEPROMs (electrically eraseable programmable read-only memories). Since writing the memory involves pulling the floating gate either to the supply voltage or to ground, the EEPROM cell cannot be read during the write process. Excess charge is typically added to the floating gate to compensate for this lack of memory state feedback. Although excess charge is acceptable when writing a binary valued “digital” memory, where the exact quantity of charge is irrelevant once it exceeds the amount necessary to completely switch the device to one of its two binary states, uncertainty in the amount of charge applied to an analog memory cell may result in significant memory error. Because the memory-write process is not self-convergent, analog EEPROMs use iterative writes. This need has not been satisfied adequately by commercial nFET (n-channel field effect transistor) EEPROMs, primarily because conventional EEPROM transistors do not permit simultaneous memory reading and writing. Most analog EEPROM implementations require iterative writes: first the memory is written, then it is read; the written and read values then are compared, and the error is used to write a correction. This cycle is repeated until the error is within prescribed bounds.
Hot-electron injection is a process whereby electrons near the surface of a semiconductor acquire more than about 3.1 eV of energy, typically by acceleration in an electric field, and then surmount the silicon/oxide barrier. Once in the silicon dioxide conduction band, an electric field applied across the oxide carries these electrons to the floating gate. There are a number of ways of accomplishing hot-electron injection.
One source for a high electric field is the collector-to-base depletion region of either a vertical or lateral bipolar junction transistor (BJT). An example of a lateral BJT used in a similar application is shown in U.S. Pat. No. 4,953,928 to Anderson, et al. Although this device is suitable for analog learning applications, each learning cell requires both an injection BJT and a MOSFET (metal oxide semiconductor field effect transistor), the former to effect hot-electron injection and the latter to read the stored charge. A reduction in the number of transistors per cell would be highly desirable.
Another source for a high electric field is in the channel region of a split-gate n− type MOSFET. Split-gate injectors, as shown and described in U.S. Pat. No. 4,622,656 to Kamiya, et al., contain two partially overlapping gate regions at very different voltages. The resulting surface potential drops abruptly at the interface between the two gates, creating a high electric field localized in this small region of the transistor channel. Unfortunately, since the control gate modulates the injection rate but does not receive the injected charge, the memory cannot be both written and read simultaneously. Such a device is acceptable for digital EEPROMs but is unsuitable for analog learning cell or analog memory applications.
A third source for high electric field is the drain to source voltage dropped across the channel region of an above-threshold sub-micron n− type MOSFET. The disadvantage of this device is that in order to achieve injection, both the drain and gate voltages must exceed approximately 2.5 volts which results in high channel current and consequent high power consumption.
A fourth source for high electric field is the drain to channel depletion region formed in an n− type MOSFET. In a conventional MOSFET, as depicted in FIGS. 4-5, this field only exists when the drain-to-source voltage exceeds 2.5 volts and the transistor is operated at or near its subthreshold regime. Since subthreshold MOSFET gate voltages are typically less than one volt, electrons injected into the gate oxide encounter a large electric field directed towards the transistor drain, opposing their transport to the floating gate. The resulting charge transfer to the floating gate is negligibly small as can be seen in the FIG. 5 energy band diagram of the transistor of FIG. 4.
Accordingly, there is a need for an improved silicon analog memory cell (useable as well for digital value storage) which can be written and erased, written and read simultaneously, and realized in a single device.
Additionally, implementations which are suitable in standard logic CMOS processes are preferable. A logic CMOS process is any silicon process capable of fabricating p− type and n− type FETs with the minimal number of processing steps. Additional steps, for example double-polysilicon processes, increase the cost of fabricating such memory devices.